NVIDIA networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AI’s Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!
We’re looking for a hardware u/architect for our switch division. In this position, as part of a small (~6 employees) elite team, you will have the chance to define the architecture of NVIDIA’s next generation switch product lines, both Ethernet and InfiniBand. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design and platform teams.
What you’ll be doing:
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Learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and verification engineers.
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Define the implementation of the most sophisticated features of our next products, balancing architecture requirements with backend, execution, and design considerations.
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Understand our system requirement and help define the POR of our switch product line.
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Face the most challenging Full-Chip correctness and performance issues, which cannot be handled by the units’ designers as they require full cross-unit understanding of the chip.
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Work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
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Thoroughly understand Ethernet, InfiniBand and NvLink protocols.
What we need to see:
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B.Sc. in Electrical Engineering or equivalent experience
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More than 7+ years of experience in ASIC design
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At least 4 years of hands on experience in writing Verilog/VHDL
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Strong analytic capabilities, and passion for solving logical issues
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Ability to drive complex activities involving many interfaces and teams
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Good communications skill
Ways to stand out from the crowd:
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Knowledge in switching fabrics with strict performance requirements. (Networking, SOC connectivity, etc)
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Experience as an HW-architect.
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Familiar with working on large high-end ASICs.
